1. Field of the Invention
The present invention relates to a bus encoding/decoding method and a corresponding bus encoder/decoder. More particularly, the present invention relates to a bus encoding/decoding method and a corresponding bus encoder/decoder capable of reducing the power consumption of an input/output (I/O) circuit.
2. Description of Related Art
Currently, energy and environment issues are global concerns. For a computing system, pursuing reducing the power from the chip level to the system level is an important issue. When the power of the computing system increases, the overhead for powering and cooling the system will increase at an even higher rate. Therefore, chip manufacturers, such as IBM, Intel, AMD, and Sun, for example, are trying to reduce the power consumed by their chips and systems.
The computing system generally consists of a processor and a peripheral input/output (I/O) circuit. Accordingly, the power consumption of the computing system consists of the power of the processor and the power of the I/O circuit (referred to here as I/O power). Currently, many methods for reducing the power of the processor have been proposed as approaches for reducing the power of the computing system. For example, Intel has proposed a power source managing method which reduces the operating voltage and the frequency of the central processing unit (CPU) when the load of the CPU is low so as to reduce the power requirement of the CPU. However, this method does not mention reducing the I/O power. The I/O power is about 50 percent of the power of the computing system when the Intel method is not used. However, when the method is used, the ratio of the I/O power increases to 70 percent or higher to result in an imbalance between the processor power and the I/O power, because the processor power is reduced to about 10 percent of its original value and the I/O power remains relatively unchanged. Moreover, it has been found that the percentage of the I/O power for a mobile device can be up to 80 percent of the total. Therefore, as another approach for reducing the power of the computing system, it is increasingly important to reduce the I/O power.
The I/O power consists of a dynamic I/O power and a static I/O power. It has been proven that the dynamic I/O power can be represented by the following equation:P=C·N·VDD2·f  (1)where P is the dynamic I/O power, C is the equivalent capacitance of the I/O circuit, VDD is the operating voltage, f is the operating frequency, and N is the bus transition number. The bus transition number refers to the number of times of level transitions (or inversions) of a bus when data having different logic values are transmitted via the bus; specifically, for example, after a first bit having a first logic value (0 or 1) is transmitted via the bus, it is necessary to switch (or invert) the level on the bus from the first logic value to a second logic value to transmit a second bit if the second bit to be transmitted next has the second logic value (1 or 0), different from the first logic value, which corresponds to one bus transition; when one word is transmitted via the bus, the bus transition number is the total number of the level transmission at the time of transmitting the word. It is shown in the above equation (1) that the I/O power is directly proportional to the bus transition number N when the other conditions remain unchanged. Thus, it is also possible to reduce the I/O power, other than by reducing the operating voltage and the frequency, by decreasing N.
Many methods have been proposed to decrease the bus transition number. For example, a method was proposed in “Bus-invert Coding for Low-Power I/O”, Mircea R. Stan and Wayne P. Burleson, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 3, Issue 1 (March 1995) pp. 49-58.
In the above method, after a word D0 (64 bits) is transmitted, it is checked whether more than one half of the bits of the word D0 need to be switched to transmit the next word D1 (64 bits). That is, it is checked whether the number of different bits between the word D0 and the word D1 are more than one half (32 bits) of the 64 bits. If so, all bits of the word D1 are switched (or inverted) so that at most 32 instance of bus transition are required. Meanwhile, transform information is generated to indicate whether the transmitted word is inverted, and an additional signal line is used to transmit the transform information. This method can decrease the bus transition number, but an optimum result may not be obtained by processing all data using one transform mode (i.e., inverting), because it is difficult to predict the mode of the transmitted data. Moreover, this method needs to add an additional signal line, which will result in incompatibility of the circuit design.
As to other methods proposed to decrease the bus transition number, they either need an additional signal line, or need a complicated algorithm to deduce the bus encoding scheme, or are only applicable for an address bus. None of these methods consider the encoding and the transmitting of data from a temporal and spatial viewpoint.
Therefore, a bus encoder/decoder and a bus encoding/decoding method for reducing the I/O power by decreasing the bus transition number are needed. These need to be not only applicable for an address bus, but also applicable for a data bus, and have good compatibility with existing systems.